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SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
May 2008
FIN212AC
12-Bit Serializer Deserializer with Multiple Frequency Ranges
Features
Low Power Consumption Low Power, Proprietary, CTLTM I/O Serial Interface Wide PLL Input Frequency Range Wide Parallel Supply Voltage Range: 1.65 to 3.6V Low Power Core Operation: VDDS/A=2.5 to 3.6V Built-in LV-CMOS Voltage Translation Capability with no External Components Adjustable Parallel Edge Rate Operates as Serializer or Deserializer Standby Power-Down Mode Support Built-in Differential Termination
Description
The FIN212AC SerDesTM is a low-power serializer / deserializer optimized for use in cell phone displays and camera paths. The device reduces a 12-bit data path to four wires. The device can be configured as a serializer or deserializer through the DIRI pin, minimizing component types in the system. For camera applications, an additional master clock can be passed in the opposite direction of data flow. The device utilizes Fairchild's proprietary ultra-low power, low-EMI technology. LV-CMOS parallel output buffers have been implemented with slew rate control to adjust for capacitive loading and to minimize EMI. The device also supports an ultra-low power-down mode for conserving power in battery-operated applications. The device is available in a 5x5mm MLP package to attach directly to a flex circuit, or in two choices of BGA, where space constraints are a concern.
Applications
8-Bit LCD Displays for Cell Phones 8/10-Bit Cell Phone Camera Interface 8-Bit LCD Displays for Printers
Related Application Notes
AN-5058 SerDesTM Family Frequently Asked Questions AN-5061 SerDesTM Layout Guidelines
Ordering Information
Order Number FIN212ACMLX FIN212ACGFX FIN212ACBFX Operating Temperature Range -30 to 70C -30 to 70C -30 to 70C Package Description 32-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 5mm Square 42-Ball Ultra Small-Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5 x 4.5mm Wide, 0.5mm Ball Pitch 36-Ball Ultra Small Scale Ball Grid Array (USS-BGA), 2.5mm Square, 0.4mm Ball Pitch (Preliminary) Packing Method Tape & Reel Tape & Reel Tape & Reel
All standard Fairchild Semiconductor products are RoHS compliant and many are also "GREEN" or going green. For Fairchild's definition of "green" please visit: http://www.fairchildsemi.com/company/green/rohs_green.html
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
www.fairchildsemi.com
SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Pin Definitions
Pin DP[1:12] CKREF STROBE CKP DSO+(DSI-) DSO-(DSI+)
(1)
I/O type CMOS-I/O CMOS-IN CMOS-IN CMOSOUT DIFF-I/O DIFF-IN DIFF-OUT CMOS-IN CMOS-IN CMOS-IN CMOS_IN CMOS_IN IN OUT Supply Supply Supply Supply
# of Pins 12 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 0
Description of Signals LV-CMOS Parallel I/O. Direction controlled by DIRI pin. LV-CMOS clock input and PLL reference. LV-CMOS strobe input for latching data into the serializer. LV-CMOS word clock output. CTL Differential serial I/O data signals. DS(I)+: Positive signal of DS(I) pair; DS(I)-: Negative signal of DS(I) pair. CTL Differential deserializer input bit clock. CKSI+: Positive signal of CKSI pair; CKSI-: Negative signal of CKSI pair. CTL Differential serializer output bit clock. CKSO+: Positive signal of CKSO pair; CKSO-: Negative signal of CKSO pair. DIRI=1: signals are used to define frequency range for the PLL. DIRI=0: Signals are used to define the edge rate of the deserializer parallel I/Os. DIRI=1: PLL0 signal is used to divide or adjust the serial frequency. DIRI=0: PWS0 signal is used to set the width of the CKP output pulse. DIRI=1: PLL1 Signal is used to divide the serial frequency. DIRI=0: PWS1 pin controls the output pulse width. DIRI=1: TEST=0, Normal Operation. DIRI=0: Termination enable functionality for deserializer. XTRM=0 Internal termination. XTRM=1 External termination required. Ground this pin for serializer. Adjusts CTL drive for serializer. Ground this pin for deserializer. LV-CMOS Control Input. Used to control direction of data flow: DIRI= "1" Serializer, DIRI="0" Deserializer LV-CMOS Output. Inversion of DIRI in normal operation mode. Power supply for parallel I/O and translation circuitry. Power supply for core and serial I/O. Power supply for analog PLL circuitry. Ground center pad, ground D4, E3 and NCs for 42-ball BGA. Ground B5, C2, C4 for 36-ball BGA.
(2)
CKSI+, CKSICKSO+, CKSOS0, S1 PLL0(PWS0) PLL1(PWS1) TEST / (XTRM) CTL_ADJ (GND) DIRI /DIRO VDDP VDDS VDDA GND
Notes: 1. () Indicate deserializer functionality when DIRI=0. 2. The DS serial port pins are arranged such that when one device is rotated 180 degrees from the other device, the serial connections properly align without the need for any traces or cable signals to cross. Other layout orientations may require that traces or cables cross. 3. All unused LV-CMOS input signals should be connected to GND or VDDP. Signals can be connected directly to the rail or through a resistor. 4. All unused LV-CMOS output signals should be allowed to float.
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
www.fairchildsemi.com 2
SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Pin Configurations
DP[3] DP[2] DP[1] (XTRM) CTL_ADJ STROBE CKREF /DIRO
DP[4] DP[5] DP[6] VDDP CKP DP[7] DP[8] DP[9]
1 2 3 4 5 6 7 8
DP[10] DP[11] DP[12] PLL1(PWS1) PLL0(PWS0) S1 S0 VDDA 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
24 23 22 21 20 19 18 17
CKSO+ CKSODSO+/DSIDSO-/DSI+ CKSICKSI+ DIRI VDDS
Figure 1.
Pin Assignments for 32-Pin MLP (5x5mm, .5mm Pitch, Top View)
1 A B C D E F G
2
3
4
5
6 A B C D E F G
1 DP4 DP6 CKP N/C DP8 DP10 DP12
2 DP2 DP5 N/C DP7 DP9 DP11 n/c
3 XTRM DP1 DP3 VDDP GND n/c
4 CTL_ADJ n/c n/c GND VDDS VDDA
5 n/c STROBE CKSO+ DSO-/DSI+ CKSI+ n/c S1
6 CKREF /DIRO CKSODS0+/DSICKSIDIRI S0
PLL1(PWS1) PLL0(PWS0)
Figure 2.
( 1 A B C D E F 2 p 3 ) 4
Pin Assignments for 42 BGA (3.5x4.5mm, .5mm Pitch, Top View)
5
6 A B C D E F
1 DP4 DP6 CKP DP7 DP9 DP11
2 DP2 DP5 GND DP8 DP10 DP12
3 DP1 DP3 VDDP GND PLL1(PWS1) / PLL0(PWS0)
4 (XTRM) CTL_ADJ GND VDDS S0 S1
5 STROBE GND CKSO+ DSO-/DSI+ CKSI+ VDDA
6 CKREF /DIRO CKSODS0+/DSICKSIDIRI
Figure 3.
Pin Assignments for 36 BGA (2.5x2.5mm, .4mm Pitch) Preliminary
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
www.fairchildsemi.com 3
SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Control Logic Circuitry
Mode PLL0 PLL1 S1 S0 0 X X 0 0 1 1 0 0 1 1 0 0 0 1 1 X X 0 1 2 1 0 1 0 2 0 0 1 0 2 X X 1 0 3 1 0 1 1 3 0 0 1 1 3 X X 1 1 Table 1. Control Logic Circuitry DIRI X 1 1 0 1 1 0 1 1 0 Description Power-Down Mode 12-Bit Serializer, Standard Clocking, 20MHz to 40MHz CKREF 12-Bit Serializer, Over-Clocked PLL, 19MHz to 38.2MHz CKREF 12-Bit Deserializer 12-Bit Serializer, Standard Clocking, 5MHz to 14MHz CKREF 12-Bit Serializer, Over-0Clocked PLL, 4.7MHz to 13.3MHz CKREF 12-Bit Deserializer 12-Bit Serializer, Standard Clocking, 8MHz to 28MHz CKREF 12-Bit Serializer, Over-Clocked PLL, 9.5MHz to 26.7MHz CKREF 12-Bit Deserializer No-Divide mode should be used for standard 8-bit pixel interface where the STROBE and CKREF frequencies are identical. Divide-by-2 and Divide-by-3 modes are useful in microcontroller interfaces where the CKREF frequency is significantly higher than the required STROBE frequency. DIRI=1 PLL1 PLL0 0 0 1 0 1 0 Serializer Frequency Multiplier 7.3x 7x 3.5x Over-clocking No Divide Divide by 2 Divide by 3
[DIRI] Direction Logic: The FIN212 can be configured as a 12-bit serializer or deserializer based on the state of the DIRI signal. When DIRI is 1, the device is a serializer. When DIRI is 0, the device is a deserializer. The /DIRO signal is an inversion of the DIRI signal. The /DIRO signal of the master can be used to drive the DIRI signal of the slave in applications where the interface needs to be turned around. [S0, S1] Mode Select: The mode select signals, S1 and S0, are used for different purposes when the device is a serializer or a deserializer. For the serializer, the pins need to be set to the correct value of the input CKREF Frequency range. For the deserializer the signals are used to select an edge rate value. The fastest edge rates correspond to the highest frequency mode. This relationship is maintained for all modes. Mode # 0 1 2 DIRI=0 S1 0 0 1 S0 0 1 0 Frequency Range Power-Down FAST SLOW MEDIUM
1 1 2.3x Table 3. Frequency Multipliers
Internal STROBE Filter: When the PLL starts, the STROBE signal is internally held off until the PLL is locked. This prevents any spurious data from being passed through the device. [PWS0, PWS1] Pulse Width Adjust Circuitry: The word clock strobe output (CKP) pulse width can be adjusted through the PWS0 and PWS1 signals. The signals can be used to lengthen the width of the LOW pulse or invert the pulse in RGB applications with a 50% duty cycle. DIRI=0 PWS1 PWS0 0 0 1 1 0 1 0 1 Low Time (Bits) No Divide 7 7 13 17 Polarity (CKP Read Edge) LH HL LH LH
3 1 1 Table 2. Deserializer Edge Rates
[PLL0, PLL1] PLL Frequency Select Signals: The PLL1 and PLL0 signals provide additional flexibility in generating the serial clock frequency. The PLLn signals only function when the device is a serializer (DIRI=1). When the device is a slave, these pins are used for pulse width adjustment. Over-clocking mode is used when the input reference clock has been implemented with significant spread spectrum. Over-clocking allows the serializer to tolerate a large amount of CKREF frequency spread.
Table 4. Pulse Width Adjust Circuitry at Serial CLK Period
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
www.fairchildsemi.com 4
SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Power-Down Functionality: When both S1 and S0 signals are 0, regardless of the state of the DIRI signal, the FIN212AC resets and powers down. The power-down mode shuts down all internal analog circuitry, disables the serial input and output of the device, and resets all internal digital logic. Table 5 indicates the state of the output buffers in PowerDown mode. Signal Pins DP[10:1] DP[12:11] CKP STROBE CKREF DIRI=1 Inputs Disabled Inputs Disabled HIGH Input Disabled Input Disabled DIRI=0 Outputs HIGH-Z Outputs HIGH-Z Outputs HIGH-Z Input Disabled Input Disabled 1
[CTL_ADJ] CTL Drive Adjustment: The drive characteristics of the CTL I/O can be adjusted through the CTL_ADJ pin. Standard-level CTL drive is provided when the CTL_ADJ pin is zero. High- level drive is provided when CTL_ADJ pin is HIGH. Highdrive should be used in noisy environments or when driving cables longer than 20cm. When in high-drive mode, CTL drive increases by approximately by 50%. CTL_ADJ 0 Description Standard CTL Drive
1 High CTL Drive Table 6. CTL_ADJ Functionality [(/XTRM]] Test / XTRM Mode Functionality: For the deserializer, the (XTRM) signal can be used to enable or disable the internal termination resistor on the CKS and DS signals of the deserializer. When the internal termination is disabled, an external termination resistor is required for the CTL I/O to operate properly. (XTRM) 0 1 DIRI=0 (/XTRM) Internal Termination External Termination
/DIRO 0 Table 5. Output States
When an input is disabled, it does not draw current, regardless of the state or level of the input signal. All of the LV-CMOS inputs must remain driven during power-down to ensure a low-power state Turn-Around Functionality: The device passes and inverts the DIRI signal asynchronously to the /DIRO signal. Care must be taken by the system designer to ensure that no contention occurs between the deserializer outputs and the other devices on this port. Optimally the peripheral device driving the serializer should be put into a HIGH-impedance state prior to the DIRI signal being asserted. When a device with dedicated data outputs turns from a deserializer to a serializer, the dedicated outputs remain at the last logical value asserted. This value only changes if the device is once again turned around into a deserializer and the values are overwritten. Strobe Pass-Through Mode: For some applications, it is desirable to pass a word clock across a differential signal pair in the opposite direction of serialization. The FIN212 supports this mode of operation. The following describes how to enable this functionality for an images sensor (see Figure 5). Deserializer Configuration (DIRI=0) 1. 2. 1. Connect CKREF(BGA pin A6) to GROUND Connect master clock to STROBE (BGA pin B5) CKSI passes master clock to CKP output (BGA pin C1)
Table 7. (/XTRM) Functionality
Serializer Configuration (DIRI=1)
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
www.fairchildsemi.com 5
SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Serializer Operation Mode (DIRI=1)
The serializer configurations are described in the following sections. The basic serialization circuitry works similarly in all modes, but the actual data and clock streams differ if the frequency of CKREF is the same as or greater than the STROBE frequency. When CKREF equals STROBE, the CKREF and STROBE signals are physically connected together and are one signal. When CKREF does not equal STROBE, each signal is distinct and CKREF must be running at a frequency high enough to avoid any loss of data condition. CKREF must never be a lower frequency than STROBE. For proper serialization, the PLL should be stable and locked prior to sending valid data. For the following modes, refer to Table 1. MODE 1,2,3; PLL1=0, PLL0=1; CKREF Equals STROBE This mode is typically used when sending pixel data at a constant rate. Data is captured on the rising edge of the STROBE signal and serialized. The serial CLK frequency is exactly seven times the clock frequency. For example, a CKREF frequency of 10MHz results in a serial CLK frequency of 70MHz and a data transfer rate of 140Mbps. The serialized data stream is synchronized and sent source synchronously with a bit clock. MODE 1,2,3; PLL1=0, PLL0=1; CKREF Does Not Equal STROBE For microcontroller interfaces, a reference clock at the same frequency as the strobe is typically not available. Data transfers are typically not synchronous. To accommodate this type of transfer, a reference clock of a higher frequency than the fastest strobe frequency must be provided to the CKREF signal. The CKREF clock signal must be continuously running for as long as data is being transferred. The actual serial transfer rate is dependent on the CKREF and the parallel transfer rate depends on the STROBE frequency. A data value of zero is sent when no valid data is present in the serial bit stream. The operation of the serializer otherwise remains the same. The exact frequency that the reference clock needs to run is dependent upon the stability of the CKREF and STROBE signal. If the source of the CKREF signal implements spread spectrum technology, the minimum frequency of this spread spectrum clock should be used in calculating the ratio of STROBE frequency to the CKREF frequency. Similarly if the STROBE signal has significant cycle-to-cycle variation, the maximum cycle-to-cycle time needs to be factored into the selection of the CKREF frequency. A STROBE frequency of 7MHz and a CKREF of 11MHz results in serial CLK frequency seven times the CKREF (77MHz) and a data transfer rate of 154Mbps. MODES (1,2,3); PLL1=1,PLL0=0 (Divide-by-2) or PLL1=1,PLL0=1 (Divide-by-3) For some microcontroller applications, the available reference frequency is significantly faster than the STROBE frequency required for the application. To more closely match the serial frequency with the strobe, the reference frequency can be divided by two or three. The serializer works identically to when CKREF is not equal to STROBE. Refer to the Deserializer Operation Mode section below for details.
Deserializer Operation Mode
The operation of the deserializer is dependent upon the data received on the DSI data signal pair and the CKSI clock signal pair. The following sections describe the operation of the deserializer under two distinct serializer source conditions. References to the CKREF and STROBE signals refer to the signals associated with the serializer device used to generate the serial data and clock signals. When operating in this mode, the internal serializer circuitry is disabled, including the parallel data input buffers. If there is a CKREF signal provided, the CKSO serial clock continues to transmit bit clocks. DIRI = 0; Serializer Source: CKREF Equals STROBE When the DIRI signal is asserted LOW, the device is configured as a deserializer. Data is captured on the serial port and deserialized through a bit clock sent with the data. The falling edge of CKP occurs coincident with the parallel data transition. DIRI=0; Serializer Source: CKREF Does Not Equal STROBE The logical operation of the deserializer remains the same whether CKREF is equal in frequency to STROBE or at a higher frequency than STROBE. The duty cycle of CKP varies based on the ratio of the frequency of the CKREF signal to the STROBE signal. The average frequency of the CKP signal is equal to the STROBE frequency. The falling edge of CKP is coincident with data transition. The LOW time of the CKP signal is set by the state of the PWS1 and PWS0 signals.
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
www.fairchildsemi.com 6
SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Pulse Width Calculations
Pulse Width Low Tpwl = (divOut*Pwdth)/(CKREF*14) To meet minimum pulse width specification, divOut*PwdthTpwl*(TCKREF*14). Bit times based on PWS0, PWS1 (Pwdth = 7, 13, 17), divide by divOut = 0.954, 1, 2, 3. Example: Tpwl=60ns CKREF=26MHz CKP Pulsewidth = (2*13)/(26MHz*14) if DivOut=2, Pwdth=13 bitTimes=26. Tpwl=71.4ns
Serializer Setup PLL1 PLL0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Deserializer Setup PWS1 PWS0
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
PLL DivOut
0.954 0.954 0.954 0.954 1 1 1 1 2 2 2 2 3 3 3 3
Pwidth
7 7 13 17 7 7 13 17 7 7 13 17 7 7 13 17
CKP-PWL Bit Times 6.7 6.7 12.4 16.2 7 7 13 17 14 14 26 34 21 21 39 51
CKREF Frequency 19.2MHz 26Mhz 24.8 24.8 46.1 60.3 26.0 26.0 48.4 63.2 52.1 52.1 96.7 126.5 78.1 78.1 145.1 189.7
(5)
18.3 18.3 34.1 44.6 19.2 19.2 35.7 46.7 38.5 38.5 71.4 93.4 57.7 57.7 107.1 140.1
Table 8. CKP Pulse Widths (in nanoseconds) for Standard Cell Phone Operating Frequencies
Note: 5. CKP Pwidth assumes minimal slew rate at the 50% transition point.
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
www.fairchildsemi.com 7
SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Application Diagrams
The following application diagrams illustrate the most typical applications for the FIN212 device. Specific configurations of the control pins may vary based on the needs of a given system. The following recommendations are valid for all of the applications shown.
FIN212 Serializer
VDD1 VDD 2.775
Baseband Microprocessor
FIN212 Deserializer
VDD2
LCD Display Module
D3
E4
F4
E4
F4
D3
VDDP VDDS/A PIXEL CLK
NC A6 B5 C1
VDDS/A VDDP CKP C1 STROBE B5 CKREF A6 DP[8:1] B3:E1 DP[9] E2 CKSIDP[10] F1 DP[12:11] G1:F2 D6 DSO-/DSI+ D5 DSO+/DSIC6 XTRM A3 CKSONC C5 DIRI F6 NC CKSO+ PWS1 G3 NC B6 /DIRO PWS0 G4
E5 CKSI+ E6
CKREF STROBE CKP
PIXEL CLK
DATA[7:0] HSYNC VSYNC
DP[8:1] DP[9] CKSO+ F1 DP[10] CKSOG1:F2 DP[12:11] DSO+/DSIDSO-/DSI+ CKSI VDD1 CKSI+ F6 DIRI
E2 G3 G4
B3:E1
DATA[7:0] HSYNC VSYNC
NC
C5 C6 D6 D5 E6 NC E5 NC
PLL1 PLL0 S1 G5
/DIRO B6 NC
S0 G6
S1 G5
S0 G6 /RES
/RES
Figure 4.
8-Bit RGB Application (Example Shows BGA 42-Pin Package)
Serializer Configuration:
PLL Frequency Mode: MODE 3 (S1=S0=1) 10-30MHz Frequency Range PLL Divide Mode: Over-Clocked Mode (PLL1=PLL0=0); 7.3 Serial Frequency Multiplier
Deserializer Configuration:
Edge Rate Mode: Medium MODE 3 (S1=S0=1) Pulse Width Mode: Standard Non-Inverting, (PWS1=PWS0=0) Pulse Width; 3.5 x Serial CLK Period Pixel CLK is used to STROBE Display Pin number for BGA packages
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
www.fairchildsemi.com 8
SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Application Diagrams (Continued)
FIN212 Serializer
VDD VDD2 2.775
Baseband Microprocessor Camera Interface
A6
FIN212 Deserializer
VDD1
D3
E4
F4
E4
F4
D3
CMOS Image Sensor 1.3MPixel
VDDP VDDS/A CKREF STROBE CKP DP[8:1] DP[9] CKSO+ DP[10] CKSODP[12:11] DSO+/DSIDSO-/DSI+ CKSI XTRM CKSI+ DIRI PWS1 PWS0 S1 G5
/DIRO
VDDS/A VDDP CKP C1 STROBE B5 CKREF A6 DP[8:1] B3:E1 DP[9] E2 DP[10] F1 CKSIDP[12:11] G1:F2 D6 DSO-/DSI+ D5 DSO+/DSIC6 CKSOC5 DIRI F6 CKSO+ PLL1 G3 NC B6 /DIRO PLL0 G4
E5 CKSI+ E6
MASTER CLK PIXEL CLK YUV[7:0] HSYNC VSYNC
NC
B5 C1 B3:E1 E2 F1 G1:F2
MASTER CLK PIXEL CLK
DATA[7:0] HSYNC VSYNC
C5 C6 D6 D5 E6 E5 B6 NC
A3 F6 G3 G4
VDD2
S0 G6
S1 G5
S0 G6 /RES
/RES
Figure 5.
8-Bit YUV 1.3MPixel CMOS Imager (Example Shows BGA 42-Pin Package)
Serializer Configuration:
PLL Frequency Mode: MODE 3 (S1=S0=1) 10-30MHz Frequency Range PLL Divide Mode: Standard Not Over-Clocked (PLL1=0, PLL0=1) Multiplier 7x Master Clock Bypass Mode: (clock passes from CKSI to CKP, see the Strobe Pass-through Mode section)
Deserializer Configuration:
Edge Rate Mode: Fast MODE 1 (S1=0, S0=1) Pulse Width Mode: Standard Non-Inverting, (PWS1=PWS0=0) Pulse Width; 3.5 x Serial CLK Period Master Clock Bypass Mode: Clock passes from STROBE to CKSO
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
www.fairchildsemi.com 9
SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Application Diagrams (Continued)
Baseband Microprocessor FIN212 Serializer
VDD1 VDD 2.775
FIN212 Deserializer
VDD2
LCD Primary Display /WE DATA[7:0] C/D/CS /RES
D3
E4
F4
E4
F4
D3
VDDP VDDS/A SYS CLK /WE
NC A6 B5 C1
VDDS/A VDDP CKP C1 STROBE B5 CKREF A6 DP[8:1] B3:E1 DP[9] E2 E5 DP[10] F1 NC CKSI+ E6 CKSIDP[11] F2 DP[12] G1 D6 DSO-/DSI+ VDD2 D5 DSO+/DSIF6 C6 DIRI CKSONC G3 PWS1 NC C5 CKSO+ G4 PWS0 NC B6 /DIRO S1 S0 G5 G6
CKREF STROBE CKP DP[8:1] DP[9] DP[10] CKSO+ DP[11] CKSODP[12] DSO+/DSIDSO-/DSI+ CKSI DIRI CKSI+ PLL1 PLL0 /DIRO S1 S0 G5 G6
DATA[7:0] A0 /CS0 /CS1
B3:E1 E2 F1 F2 G1
C5 C6 D6 D5 E6 NC E5 NC B6 NC
LCD Sub Display
VDD1
F6 G3 G4
/RES
/WE DATA[7:0] C/D/CS /RES
Figure 6.
Dual Display with 8-Bit WRITE-Only Microcontroller Interface (Example Shows BGA 42-Pin Package)
Serializer Configuration:
PLL Frequency Mode: MODE 1 (S1=0, S0=1) CKREF=26MHz STROBE Frequency = 10 MHz PLL Divide Mode: Divide-by 2 (PLL1=1, PLL0=0) Multiplier x 3.5
Deserializer Configuration:
Edge Rate Mode: SLOW MODE 1 (S1=1, S0=0) Pulse Width Mode: 13-Bit Time Mode (PWS1=PWS0=0) (~71.4ns)
Additional Application Information
Flex Cabling: The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex cable. The following best practices should be used when developing the flex cabling or Flex PCB. Keep all four differential Serial Wires the same length. Do not allow noisy signals over or near differential serial wires. Example: No LVCMOS traces over differential serial wires. Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom. Design goal of 100-ohms differential characteristic impedance. Do not place test points on differential serial wires. Use differential serial wires a minimum of 2cm away from the antenna. For additional applications notes or flex guidelines see your sales rep or contact Fairchild directly.
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
www.fairchildsemi.com 10
SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD Supply Voltage All Input/Output Voltage CTL Output Short-Circuit Duration TSTG TJ TL ESD Storage Temperature Range Maximum Junction Temperature Lead Temperature (Soldering, four seconds) Human Body Model, JESD22-A114, Serial I/O Pins Human Body Model, JESD22-A114, All Pins Charged Device Model, JESD22-C101 Parameter Min. -0.5V -0.5 Continuous -65 +150 +260 14 8 2 +150 C C C kV kV kV Max. +4.6 VDD+0.5 Unit V V
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VDDA, VDDS VDDP TA VDDA-PP Supply Voltage Supply Voltage Operating Temperature Supply Noise Voltage Parameter Min. 2.5 1.65 -30 100 Max. 3.6 3.60 +70 Unit V V C mVPP
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
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SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
DC Electrical Characteristics
Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol LVCMOS I/O VIH VIL VOH Input High Voltage Input Low Voltage IOH=-2.0mA, S1=0,S0=1 Output High Voltage IOH=-0.4mA, S1=1,S0=0 IOH=-1.0mA, S1=1,S0=1 IOL=2.0mA, S1=0,S0=1 VOL IIN Output Low Voltage Input Current Output HIGH Source Current Output LOW Sink Current Input Voltage Ground (7) Offset CKS Internal Receiver Termination Resistor DS Internal Receiver Termination Resistor VID= 50mV, VIC= 925mV, DIRI = 0 VID=50mV, VIC= 925mV, DIRI = 0 80 80 IOL=0.4mA, S1=1,S0=0 IOL=1.0mA, S1=1,S0=1 VIN= 0V to 3.6V CTL_ADJ=0 CTL_ADJ=1 CTL_ADJ=0 CTL_ADJ=1 -5.0 -2.0 -3.4 1.2 2.0 0 100 100 120 120 5.0 A DIFFERENTIAL I/O IODH IODL VGO VOS=1.0V VOS=1.0V mA mA V 0 0.25xVDDP V 0.75xVDDP VDDP V 0.65xVDDP GND VDDP 0.35xVDDP V Parameter Test Conditions Min. Typ.
(6)
Max.
Unit
RTRM
Notes: 6. Typical values are given for VDD=2.775V and TA=25 C. Positive current values refer to the current flowing into the device and negative values refer to the current flowing out of pins. Voltages are referenced to GROUND unless otherwise specified (except VOD and VOD). 7. VGO is the difference in device ground levels between the CTL driver and the CTL receiver.
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
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SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Power Supply Currents
Symbol IDD_PD Parameter VDD Power-Down Supply Current IDD_PD= IDDA + IDDS + IDDP Test Conditions S1 = S0 = 0, All Inputs at GND or VDD S1=L S0=H IDD_SER1 Dynamic Serializer Power Supply Current IDD_SER1= IDDA+IDDS+IDDP fCKREF = fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL = 0pF S1=H S0=L S1=H S0=H S1=L S0=H IDD_DES1 Dynamic Deserializer Power Supply Current IDD_DES1= IDDA+IDDS+IDDP fCKREF = fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL = 0pF S1=H S0=L S1=H S0=H 20MHz 40MHz 5MHz 14MHz 8MHz 28MHz 20MHz 40MHz 5MHz 14MHz 8MHz 28MHz Min. Typ. 0.1 13.0 19.0 9.5 17.0 11.0 20.0 10.0 14.0 8.0 9.0 9.0 12.0 Max. Unit A mA mA mA mA mA mA mA mA mA mA mA mA
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
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SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
AC Electrical Characteristics
Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol Parameter Test Conditions Min. Typ. Max. Unit
Serializer Input Operating Conditions CKREF Clock Frequency (5MHz - >40MHz) S1=0, S0=1 fCKREF = fSTRB S1=1, S0=0 S1=1, S0=1 PLL1=0, PLL0=0 fSTRB Strobe Frequency Relative to CKREF Frequency fCKREF fSTRB PLL1=0, PLL0=1 PLL1=1, PLL0=0 PLL1=1, PLL0=1 tCPWH tCPWL tCLKT tSPWH/L tSTC tHTC CKREF DC CKREF DC LVCMOS Input (8) Transition Time STROBE Pulse Width HIGH/LOW DP(n) Setup to STROBE DP(n) Hold to STROBE T=1/fCKREF T=1/fCKREF 10-90% T=1/fCKREF DIRI=1, f=5MHz Figure 7 T x /14 2.5 2.0
4
18 5 10
40 14 28 100 100 50 33 /3
1
fCKREF
MHz
% of fCKREF
0.2 0.2
0.5 0.5
0.8 0.8 20 Tx
10
T T ns
/14
ns ns ns
Serializer AC Electrical Characteristics tTCCD Transmitter Clock Input (9) to Clock Output Delay DIRI=1, fCKREF = fSTRB Figure 9 21a+1.5 23a+6.5 ns
Phase Lock Loop (PLL) AC Electrical Characteristics tTPLLS0 tTPLLD0 tTPLLD1 Serializer PLL Stabilization Time PLL Disable Time Loss of Clock PLL Power-Down Time CKREF toggling and stable 200 600 30.0 20.0 s s ns
Notes: 8. Parameter is characterized, but not production tested. 9. The average bit time "a" is a function of the serializer CKREF frequency; a=(1/f)/14.
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
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SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
AC Electrical Characteristics (Continued)
Values are provided for over-supply and operating temperature ranges, unless otherwise specified. Symbol Parameter Test Conditions Min. Typ. Max. Unit
Deserializer AC Electrical Characteristics PWS1 fSTRB = fCKREF tRCOL CKP OUT Low Time Figure 8 fSTRB = fCKREF fSTRB = .5x fCKREF fSTRB = .5x fCKREF tPDV Data Valid to CKP HIGH Output Rise/Fall Time Data (20% to 80%) 0 0 1 1 PWS0 0 1 0 1 7a-3 7a-3 13a-3 17a-3 8a-3 3.0 8.0 5.0 2.0 7.0 4.0 ns ns 7a+3 7a+3 13a+3 17a+3 8a+3 ns ns
(Rising Edge STROBE), CL=5pF Figure 8 S1=0,S0=1 CL=8pF S1=1,S0=0 S1=1,S0=1 S1=0,S0=1
tRFD
tRFC
Output Rise/Fall Time CKP (20% to 80%)
CL=8pF
S1=1,S0=0 S1=1,S0=1
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
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SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Logic Timing Controls
Symbol t PHL_DIR, tPLH_DIR tPLZ, tPHZ tDISDES tDISSER Parameter Propagation Delay DIRI to /DIRO Propagation Delay DIRI to DP Deserializer Disable Time: S0 or S1 LOW to DPTri-State Serializer Disable Time: S0 or S1 LOW to CKP HIGH Test Conditions DIRI L->H or H->L DIRI L->H or H->L DIRI=0, Figure 10 DIRI=1; S1(0) and S0(1)=H->L Min. Typ. Max. 17 25 25 25 Unit ns ns ns ns
Pin Capacitance Tables
Symbol CIN CIO CIO-DIFF Parameter Capacitance of Input Only Signals Capacitance of Parallel Port Pins DP[1:12] Capacitance of Differential I/O Signals Test Conditions DIRI=1, S1=0, S0=0, VDD=2.5V DIRI=1, S1=0, S0=0, VDD=2.5V DIRI=1, S1=0, S0=0, VDD=2.5V Min. Typ. 2.0 2.0 2.0 Max. Unit pF pF pF
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
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SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Typical Performance Characteristics
Setup Time
S TR OBE DP [1:12] Data
tS TC
Data Valid
CKP DP[1:12] Data
tPDV
Hold Time
S TR OBE DP[1:12 ] Data
tHTC
75%
tRCOP
CKP
50% 25%
50%
tRCOH
Setup: MODE0= "0" or "1", MODE1="1", SER/DES="1"
tRCOL
Setup: DIRI= 0, CKSI and DS are valid signals.
Figure 7.
Serializer Setup and Hold Time
Figure 8.
Deserializer Data Valid Time and Clock Output Parameters
tTCCD STROBE CKS CKS + CKP
VDD/2 VDIFF=0
tRCCD
VDD/2
Note: STROBE=CKREF
Figure 9.
Clock Propagation Delay
tDISDES S1 or S2
DP
Note:If S1(2) is transitioning, S2(1) must =0 for test to be valid.
Figure 10.
Deserializer Disable Timing
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
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SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Tape and Reel Specifications
MLP Embossed Tape Dimensions
Dimensions are in millimeters unless otherwise noted.
T P0 D P2 E F K0 W Wc B0
Tc A0 P1 D1 User Direction of Feed
Package
5x5 6x6
A0 0.1
5.35 5.35
B0 0.1
5.35 5.35
D 0.5
1.55 1.55
D1 Min.
1.50 1.50
E 0.1
1.75 1.75
F 0.1
5.50 5.50
K0 0.1
1.40 1.40
P1 Typ.
8.00 8.00
P0 Typ.
4.00 4.00
P2 0.5
2.00 2.00
T Typ.
0.30 0.30
TC 0/05
0.07 0.07
W 0.3
12.00 12.00
WC Typ.
9.30 9.30
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement requirements (see sketches A, B, and C).
MLP Shipping Reel Dimensions
Dimensions are in millimeters unless otherwise noted.
10 maximum Typical component cavity center line Typical component center line A0 Sketch B (Top View) 1.0mm maximum 1.0mm maximum Sketch C (Top View)
B0 10 maximum component rotation Sketch A (Side or Front Sectional View)
Component Rotation
Component Lateral Movement
Component Rotation
W2 max Measured at Hub
W1 Measured at Hub
B Min Dia C Dia D min
Dia A max
Dia N
DETAIL AA See detail AA
W3
Tape Width 8 12 16
Dia A Max. 330.0 330.0 330.0
Dim B Min. 1.5 1.5 1.5
Dia C +0.5/-0.2 13.0 13.0 13.0
Dia D Min. 20.2 20.2 20.2
Dim N Min. 178.0. 178.0. 178.0.
Dim W1 +2.0/-0 8.4 12.4 16.4
Dim W2 14.4 18.4 22.4
Dim W3 (LSL-USL) 7.9 ~ 10.4 11.9 ~ 15.4 15.9 ~ 19.4
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
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SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Tape and Reel Specifications (Continued)
BGA Embossed Tape Dimensions
Dimensions are in millimeters unless otherwise noted.
T P0 D P2 E F K0 W Wc B0
Tc A0 P1 D1 User Direction of Feed
Package
3.5 x 4.5
A0 0.1
3.85
B0 0.1
4.80
D 0.5
1.55
D1 Min.
1.50
E 0.1
1.75
F 0.1
5.50
K0 0.1
1.10
P1 Typ.
8.00
P0 Typ.
4.00
P2 0.5
2.00
T Typ.
0.30
TC 0/05
0.07
W 0.3
12.00
WC Typ.
9.3
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement requirements (see sketches A, B, and C).
BGA Shipping Reel Dimensions
Dimensions are in millimeters unless otherwise noted.
1.0mm maximum 1.0mm maximum Sketch C (Top View)
10 maximum B0 10 maximum component rotation Sketch A (Side or Front Sectional View) Typical component cavity center line Typical component center line A0 Sketch B (Top View)
Component Rotation
Component Lateral Movement
W1 Measured at Hub B Min Dia C
Component Rotation
W2 max Measured at Hub
Dia A max
Dia N
Dia D min
DETAIL AA See detailAA W3
Tape Width 8 12 16
Dia A Max. 330.0 330.0 330.0
Dim B Min. 1.5 1.5 1.5
Dia C +0.5/-0.2 13.0 13.0 13.0
Dia D Min. 20.2 20.2 20.2
Dim N Min. 178.0. 178.0. 178.0.
Dim W1 +2.0/-0 8.4 12.4 16.4
Dim W2 14.4 18.4 22.4
Dim W3 (LSL-USL) 7.9 ~ 10.4 11.9 ~ 15.4 15.9 ~ 19.4
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
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SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Physical Dimensions
0.15 C
5.00
B A
5.00 (0.76)
(0.25 )
PIN #1 IDENT
5.38 MIN
0.15 C
3.37 MAX 3.86 MIN
0.80 MAX 0.10 C (0.20)
0.20MIN X4
0.08 C
0.05 0.00 3.70 3.50
C
0.28 MAX X40
0.50TYP
SEATING PLANE
E
PIN #1 IDENT
0.45 0.35
PIN #1 ID
0.50 3.70 3.50
(DATUM B)
PIN #1 ID
(DATUM A)
0.18-0.30
0.50
0.10 0.05
CAB C
NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-220, VARIATION WHHD-4. THIS PACKAGE IS ALSO FOOTPRINT COMPATIBLE WITH WHHD-5. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994. D. LAND PATTERN PER IPC SM-782. E. WIDTH REDUCED TO AVOID SOLDER BRIDGING. F. DIMENSIONS ARE NOT INCLUSIVE OF BURRS, MOLD FLASH, OR TIE BAR PROTRUSIONS. G. DRAWING FILENAME: MKT-MLP32Arev3.
Figure 11.
32-Lead, Molded Leadless Package (MLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
www.fairchildsemi.com 20
SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Physical Dimensions (Continued)
Figure 12.
42-Ball, Ball Grid Array (BGA) Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
www.fairchildsemi.com 21
SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Physical Dimensions (Continued)
Figure 13.
36-Ball, Ball Grid Array (BGA) Package (Preliminary)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
www.fairchildsemi.com 22
SerDesTM FIN212AC -- 12-Bit Serializer Deserializer with Multiple Frequency Ranges
(c) 2006 Fairchild Semiconductor Corporation FIN212AC Rev. 1.0.6
www.fairchildsemi.com 23

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